VHDL Compiler

Name: VHDL Compiler
Rating: 4.2 (5 reviews)
Author: Ketan Appa

By: Ketan Appa App

Learn and code in VHDL

Overview

Version:

2.4

Last updated: 2026-03-10

Ranking

#548,215 ▲ 975,084

Overall

Features & Capabilities

Write VHDL code directly on your iPhone, iPad and iPod Touch! This app is ideal for learning and testing code snippets!

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

This app uses the open-source GHDL simulator (http://ghdl.free.fr). GHDL is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a synthesis tool: you cannot create a netlist with GHDL (yet).

Features:

Compile and run your program
View program output or detailed error
Custom keyboard for easy input of frequently used characters
Optimized for connecting with external physical/bluetooth keyboard
Advanced source code editor with syntax highlighting and line numbers
Open, save, import and share VHDL files.

Limitations:

Internet connection is required for compilation
Maximum program running time is 20s
One file can be run at a time
All entities should be have the same name as their files.

User Growth & Download Statistics

App

By:

Ketan Appa

Rating:

4.20

(5) 4.20

Version:

2.4 Last updated: 2026-03-10

Version code:

883208120

Creation date:

2019-04-28

Compatible devices:

Size:

19.57MB

URLs:

Website ,Privacy policy

Full description:

Source:

Apple Apps Store

Data ingested on:

2026-07-20

Compare stats and ranking:

Ranking

# 548,215 ▲ 975,084

For Developers

Monetize with App Pass Boost with Extension Booster

Contact the developer

Chrome-Stats does not own this Apple app. Please use these information below to contact the Apple app developer.

Developed by:

Ketan Appa

Apple Apps Store

https://apps.apple.com/cn/app/vhdl-compiler/id1459379888?l=en-GB

Website:

https://ratinbox.com/

User Reviews

I realized that it’s essential to limit simulation with ultimately a WAIT; statement including a clock generator with limited total time Here is a simple test setup beyond just text: Enjoy.. great job by the developer of the App and the original open source VHDL Compiler Designer ———————————————— -- Hello world program library IEEE; use IEEE.std_logic_1164.all; use std.textio.all; -- Imports the standard textio package. -- Defines a design entity, without any ports. entity hello is end hello; architecture behaviour of hello is signal index : integer:=0; signal clk : std_logic := '0'; begin process(clk) variable l : line; begin if(rising_edge(clk)) then write(l,String'("/")); writeline (output, l); end if; end process; process begin index <= index +1; clk <= not clk; wait for 1 ns; if index > 20 then wait; end if; end process; end behaviour;